1. Field of the Invention
The present invention relates to a stacked semiconductor device and a semiconductor device module, particularly to a stacked semiconductor device and a semiconductor memory module used for a high-speed signal transmission system.
2. Description of the Related Art
FIGS. 1A and 1B are diagrams showing a structure of a conventional stacked memory as a stacked semiconductor device. As shown in FIG. 1A, a stacked memory 10 has the structure in which package substrates (tapes) 12 (12-1 and 12-2) mounting memory chips 14 (14-1, 14-2) are stacked through connecting balls 17 arranged at the both sides of the package substrates 12. A lower-stage package substrate 12-1 has a BGA (Ball Grid Array) structure. Moreover, the package substrate 12 has a structure of two metal layers, and a signal wiring has a same structure as a transmission line. A signal wiring 22 on a memory module substrate (PCB) 11 is connected with a signal wiring on the lower-stage package substrate 12-1 through one of the ball terminals 16 and a via-contact 24 and then is divided into signal wirings A and B. The signal wiring A is a wiring having the length of about 3 mm to be connected to the memory chip 14-1 mounted on the lower-stage package substrate 12-1. The signal wiring B is a wiring having the length of about 5 mm to be connected to a signal wiring C of an upper-stage package substrate 12-2 through the connecting ball 17. The signal wiring C is a wiring having the length of about 6 mm to be connected to a chip pad 18-2 of the memory chip 14-2 mounted on the upper-stage package 12-2.
The topology of a signal wiring of the stacked memory 10 is as shown by FIG. 1B. The signal wiring 22 is branched into two wirings in the stacked memory 10. One of the branched wirings is connected to the lower-stage memory chip 14-1 through the short signal wiring A (about 3 mm) and the other branched wiring is connected to the upper-stage memory chip 14-2 through the long signal wiring (about 11 mm) by the signal wirings B and C. That is, the stacked memory 10 has a short wiring of about 3 mm and a long wiring of about 11 mm in the package substrate 12.
FIG. 2 is a diagram showing wiring topology when the conventional stacked memories 10 are used for a high-speed transmission memory module. This is a stroke-book (stubless) wiring topology used for a command address signal and a clock signal. The stacked memories 10 are stublessly connected in the middle of a bus wiring (transmission line) 30 serving as a signal wiring for connecting a controller 31 with a termination circuit 32. However, the signal wiring connected to the upper-stage memory chip 14-2 in the stacked memory 10 forms a long stub (up to 10 mm). Therefore, in case of a high-speed transmission system having a short signal rising time in a rage of 0.3 to 0.5 nanoseconds, ringing occurs due to signal reflection to deteriorate a waveform. Specifically, the stacked memory 10 closest to the controller 31 has a problem that the rising of a waveform is steep, so that large ringing easily occurs to deteriorate the waveform.
Japanese Laid Open Patent Application (JP-P2003-78109A) discloses a technique for a stacked memory device in which a plurality of BGA packages are stacked. The stacked memory device includes a first BGA package and a second BGA package respectively having ball bumps, a first stacking substrate, a second stacking substrate, a connection substrate, and ball bumps. The first stacking substrate includes a wiring pattern connected to the ball bumps of the first BGA package. The second stacking substrate includes a wiring pattern connected to the ball bumps of the second BGA package. The connection substrate is set between the first stacking substrate and the second stacking substrate to connect the wiring patterns contained in each stacking substrate. The ball bumps are provided on the surface opposite to the second BGA package of the second stacking substrate and connected to a pattern contained in the second stacking substrate. Moreover, in case of the stacked memory device, the first stacking substrate is adhered to the upper surface of a resin package contained in the second BGA package.
Furthermore, Japanese Laid Open Patent Application (JP-P2003-124439A) discloses a technique for a BGA stacked semiconductor module. In case of the BGA stacked semiconductor module, a plurality of circuit substrates respectively mounting semiconductor chips are arranged so as to overlap in a predetermined interval and a plurality of connection terminals are formed on the front and back surfaces of the circuit substrate. Each of the connection terminals on the front and back surfaces is made electrically conductive according to necessity, and a connection terminal on the back surface of the circuit substrate is electrically connected with a connection terminal on the front surface of a circuit substrate at the next stage by solder bump. In case of the BGA stacked semiconductor module, some of the connection terminals are improved in reliability by increasing areas of the connection terminals.
Moreover, Japanese Laid Open Patent Application (JP-P2003-273321A) discloses a technique for a semiconductor module in which a plurality of substrate structures are stacked, and semiconductor chips are stacked on the substrate. The semiconductor module has an insulating upper substrate, an insulating lower substrate, a plurality of signal lines, a first common potential wiring, a semiconductor chip, a support substrate, a first connection conductive layer, a second connection conductive layer, a third connection conductive layer, and an external connection terminal. The insulating lower substrate is arranged below the upper substrate. A plurality of signal lines are provided for the upper and lower substrates, respectively. The first common potential wiring is respectively arranged onto the upper and lower substrates to surround the signal lines in an interval. The semiconductor chips are respectively arranged to the upper and lower substrates and have electrode pads electrically connected with the signal lines and the first common potential wiring. The support substrate is provided to the lower portion of the lower substrate and has a wiring pattern formed on a surface opposite to the lower substrate. The first connection conductive layer is arranged between the upper and lower substrates to connect the signal wirings on the upper and lower substrates mutually electrically. The second connection conductive layer is arranged between the upper substrate and the lower substrate to mutually electrically connect the first common potential wirings on the upper and lower substrates. The third connection conductive layer is arranged to pass through the support substrate so as to electrically connect the first and second connection conductive layers. The external connection terminal is arranged on the wiring pattern.
Japanese Laid Open Patent application (JP-A-Heisei 5-55450) discloses a technique for a memory module constituted by stacking a plurality of memory device units. In case of this memory module, a concave portion is formed on the front surface of one side of an insulating substrate. A memory chip is arranged in the concave portion and a plurality of connection terminals are arranged in the peripheral portion of the surface of the insulating substrate. The memory module is constituted by stacking a plurality of memory device units constituted by connecting terminals with electrodes of the memory chip. A power-supply reinforcing capacitor and a termination resistance are built in one of the memory device units.
Moreover, Japanese Laid Open Patent Application (JP-A-Heisei 6-37246) discloses a technique for a configuration in which electrode wirings are formed on an insulating substrate and a plurality of semiconductor devices are mounted. The electrode wirings from a driving semiconductor device to a near passive semiconductor device are provided to have a high resistance and the electrode wirings from the driving semiconductor device to a far passive semiconductor device are provided to have a low resistance.
Furthermore, Japanese Laid Open Patent Application (JP-A-Heisei 8-51127) discloses a technique for a stacked semiconductor package. The stacked semiconductor package is constituted of a semiconductor chip, a plurality of internal leads and a plurality of external leads, an insulating film of a film carrier, a plurality of semiconductor packages, a plurality of frames, and a printing circuit board. The semiconductor chip has a plurality of bonding pads. The bonding pad and the internal lead are electrically connected through a bump on the insulating film of the film carrier to form a semiconductor chip. The semiconductor packages have a forming resin for protecting the semiconductor chip and the internal leads so that the lower surface of the semiconductor chip is exposed. The frames have a circuit pattern to be electrically connected to the external leads of the semiconductor package in order to stack the semiconductor packages. The printing circuit board has a ground land pattern to be electrically connected to the circuit pattern of each frame in common and has a noise preventing capacitor to be mounted on the land pattern under the exposed lower surface of the semiconductor chip. A plurality of conductive films and a plurality of ground terminals are provided in this stacked semiconductor package. The conductive films are formed on the exposed lower surfaces of the semiconductor chips. The ground terminals are electrically connected to the conductive films and electrically connected to the grounding land pattern of the printing circuit substrate in common.
Moreover, Japanese Laid Open Patent Application (JP-A-Heisei 11-260999) discloses a technique for a stacked semiconductor device module. In the stacked semiconductor device module, one or more circuit substrates and at least one circuit substrate are stacked by connecting the substrates by spherical metal connection members. The one or two or more circuit substrates include semiconductor devices on the upper surface or inside and the spherical metal connection members on the lower surface. At least one circuit substrate contains a plurality of passive components on the upper surface and the spherical metal connection member on the lower surface.